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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13746-2E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90360E Series
MB90362E, MB90362ES, MB90362TE, MB90362TES, MB90F362E, MB90F362ES, MB90F362TE, MB90F362TES, MB90367E, MB90367ES, MB90367TE, MB90367TES, MB90F367E, MB90F367ES, MB90F367TE, MB90F367TES, MB90V340E-101, MB90V340E-102, MB90V340E-103, MB90V340E-104
DESCRIPTION
The MB90360E-series, loaded 1 channel FULL-CAN* interface and Flash ROM, is general-purpose FUJITSU 16-bit microcontroller designing for automotive and industrial applications. Its main feature is the on-board CAN Interfaces, which conform to Ver 2.0 Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal FULL-CAN approach. With the new 0.35 m CMOS technology, Fujitsu now offers on-chip Flash ROM program memory up to 64 Kbytes. The power supply (3 V) is supplied to the MCU core from an internal regulator circuit. This creates a major advantage in terms of EMI and power consumption. The internal PLL clock frequency multiplier provides an internal 42 ns instruction execution time from an external 4 MHz clock. Also, main and sub clock can be monitored independently using the clock supervisor function. The unit features a 4-channel input capture unit 1 channel 16-bit free running timer, 2-channel UART, and 16channel 8/10-bit A/D converter as the peripheral resource. * : Controller Area Network (CAN) - License of Robert Bosch GmbH Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html "Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Copyright(c)2006-2007 FUJITSU LIMITED All rights reserved
MB90360E Series
FEATURES
* Clock * Built-in PLL clock frequency multiplication circuit * Selection of machine clocks (PLL clocks) is allowed among frequency division by 2 on oscillation clock and multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz) * Operation by sub clock : internal operating clock frequency: up to 50 kHz (for operating with 100 kHz oscillation clock divided two and devices without S-suffix only) is available * Minimum execution time of instruction : 42 ns (when operating with 4-MHz oscillation clock and 6-time multiplied PLL clock) * Clock supervisor (MB90x367x only) * Main clock or sub clock is monitored independently * Internal CR oscillation clock (100 kHz typical) can be used as sub clock * Instruction system best suited to controller * 16 Mbytes CPU memory space * 24-bit internal addressing * Wide choice of data types (bit, byte, word, and long word) * Wide choice of addressing modes (23 types) * Enhanced multiply-divide instructions with sign and RETI instructions * Enhanced high-precision computing with 32-bit accumulator * Instruction system compatible with high-level language (C language) and multitask * Employing system stack pointer * Enhanced various pointer indirect instructions * Barrel shift instructions * Increased processing speed 4-byte instruction queue * Powerful interrupt function * Powerful 8-level, 34-condition interrupt feature * Up to 8 channels external interrupts are supported * Automatic data transfer function independent of CPU Expanded intelligent I/O service function (EI2OS) : up to 16 channels * Low power consumption (standby) mode * Sleep mode (a mode that halts CPU operating clock) * Main timer mode (timebase timer mode that is transferred from main clock mode) * PLL timer mode (timebase timer mode that is transferred from PLL clock mode) * Watch mode (a mode that operates sub clock and watch timer only, devices without S-suffix) * Stop mode (a mode that stops oscillation clock and sub clock) * CPU blocking operation mode * Process CMOS technology * I/O port General purpose input/output port (CMOS output) : - 34 ports (devices without S-suffix) - 36 ports (devices with S-suffix) * Sub clock pin (X0A and X1A) * Provided (used for external oscillation), devices without S-suffix * Not provided (used with internal CR oscillation in sub clock mode) , devices with S-suffix (Continued) 2
MB90360E Series
(Continued) * Timer * Timebase timer, watch timer (device without S-suffix) , watchdog timer : 1 channel * 8/16-bit PPG timer : 8-bit x 2 channels or 16-bit x 1 channel * 16-bit reload timer : 2 channels * 16- bit input/output timer - 16-bit free-run timer : 1 channel (FRT0 : ICU 0/1/2/3) - 16- bit input capture : (ICU) : 4 channels * FULL-CAN interface : up to 1 channel * Compliant with CAN specifications Version 2.0 Part A and B * 16 message buffers are built in * CAN wake-up function * UART (LIN/SCI) : up to 2 channels * Equipped with full-duplex double buffer * Clock-asynchronous or clock-synchronous serial transmission is available * DTP/External interrupt : up to 8 channels, CAN wakeup : up to 1 channel Module for activation of expanded intelligent I/O service (EI2OS) and generation of external interrupt by external input * Delay interrupt generator module Generates interrupt request for task switching * 8/10-bit A/D converter : 16 channels * Resolution is selectable between 8-bit and 10-bit * Activation by external trigger input is allowed * Conversion time : 3 s (at 24-MHz machine clock, including sampling time) * Program patch function Address matching detection for 6 address pointers * Low voltage/CPU operation detection reset (devices with T-suffix) * Detects low voltage (4.0 V 0.3 V) and resets automatically * Resets automatically when program is runaway and counter is not cleared within interval time (approx. 262 ms : external 4 MHz) * Capable of changing input voltage for port Automotive/CMOS-Schmitt input level (initial level is Automotive in single-chip mode) * Flash memory security function Protects the content of Flash memory (MB90F362x, MB90F367x only)
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MB90360E Series
PRODUCT LINEUP
Features Type CPU System clock Sub clock pin (X0A, X1A) Clock supervisor ROM RAM capacitance CAN interface Low voltage/CPU operation detection reset Package Emulator-specific power supply * Corresponding evaluation product MB90V340E-102 No Yes LQFP-48P MB90V340E-101 MASK ROM, 64 Kbytes 3 Kbytes 1 channel No Yes MB90362E MB90362TE MB90362ES MB90362TES MB90V340E- MB90V340E101 102 Evaluation product
MASK ROM product F MC-16LX CPU
2
PLL clock multiplier ( x 1, x 2, x 3, x 4, x 6, 1/2 when PLL stops) Minimum instruction execution time : 42 ns (4 MHz oscillation clock, PLL x 6) Yes No No External 30 Kbytes 3 channels No PGA-299C Yes No Yes
* : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the Emulator hardware manual for the details. Features Type CPU MB90F362E MB90F362TE MB90F362ES MB90F362TES
Flash memory product F2MC-16LX CPU PLL clock multiplier ( x 1, x 2, x 3, x 4, x 6, 1/2 when PLL stops) Minimum instruction execution time : 42 ns (4 MHz oscillation clock, PLL x 6) Yes No Flash memory, 64 Kbytes 3 Kbytes 1 channel No Yes LQFP-48P MB90V340E-102 MB90V340E-101 No Yes No
System clock
Sub clock pin (X0A, X1A) Clock supervisor ROM RAM capacitance CAN interface Low voltage/CPU operation detection reset Package Corresponding evaluation product
4
MB90360E Series
Features Type CPU System clock Sub clock pin (X0A, X1A) Clock supervisor ROM RAM capacitance CAN interface Low voltage/CPU operation detection reset Package Emulator-specific power supply * Corresponding EVA product
MB90367E MB90367TE
MB90367ES
MB90367TES
MB90V340E- MB90V340E103 104 Evaluation product
MASK ROM product F2MC-16LX CPU
PLL clock multiplier ( x 1, x 2, x 3, x 4, x 6, 1/2 when PLL stops) Minimum instruction execution time : 42 ns (4 MHz oscillation clock, PLL x 6) Yes No (internal CR oscillation can be used as sub clock) Yes MASK ROM, 64 Kbytes 3 Kbytes 1 channel No Yes No LQFP-48P MB90V340E-104 MB90V340E-103 Yes External 30 Kbytes 3 channels No PGA-299C Yes Yes
* : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the Emulator hardware manual for the details. Features Type CPU System clock MB90F367E MB90F367TE MB90F367ES MB90F367TES
Flash memory product F2MC-16LX CPU PLL clock multiplier ( x 1, x 2, x 3, x 4, x 6, 1/2 when PLL stops) Minimum instruction execution time : 42 ns (4 MHz oscillation clock, PLL x 6) Yes No (internal CR oscillation can be used as sub clock) Yes Flash memory, 64 Kbytes 3 Kbytes 1 channel No Yes LQFP-48P MB90V340E-104 MB90V340E-103 5 No Yes
Sub clock pin (X0A, X1A) Clock supervisor ROM RAM capacitance CAN interface Low voltage/CPU operation detection reset Package Corresponding EVA product
MB90360E Series
PIN ASSIGNMENT
* MB90F362E/TE/ES/TES, MB90362E/TE/ES/TES, MB90F367E/TE/ES/TES, MB90367E/TE/ES/TES (TOP VIEW)
P82/SIN0/INT14R/TIN2
P84/SCK0/INT15R
P83/SOT0/TOT2
P44/FRCK0
X1A/P41 *1
X0A/P40 *1
P42/RX1/INT9R
P86/SOT1
P87/SCK1 38
48
AVss
47
46
45
44
43
42
41
40
39
37
P85/SIN1
P43/TX1
AVcc AVR P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6/PPGC(D) P67/AN7/PPGE(F) P80/ADTG/INT12R P50/AN8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33 32 31 30 29 28 27 26 25
P20 *2 P21 *2 P22/PPGD(C) *2 P23/PPGF(E) *2 P24/IN0 P25/IN1 P26/IN2 P27/IN3 X1 X0 C Vss
P52/AN10
P53/AN11/TIN3
P54/AN12/TOT3/INT8
P55/AN13/INT10
P56/AN14/INT11
P57/AN15/INT13
MD2
MD1
P51/AN9
(FPT-48P-M26)
*1 : MB90F362E/TE, MB90362E/TE, MB90F367E/TE, MB90367E/TE : X0A, X1A MB90F362ES/TES, MB90362ES/TES, MB90F367ES/TES, MB90367ES/TES : P40, P41 *2 : High current output port
6
MD0
RST
Vcc
MB90360E Series
PIN DESCRIPTION
Pin No. 1 2 3 to 8 Pin name AVCC AVR P60 to P65 AN0 to AN5 P66, P67 9, 10 AN6, AN7 PPGC (D) , PPGE (F) P80 11 ADTG INT12R 12 to 14 P50 to P52 AN8 to AN10 P53 15 AN11 TIN3 P54 16 AN12 TOT3 INT8 P55 to P57 17 to 19 AN13 to AN15 INT10, INT11, INT13 20 21, 22 23 24 25 26 MD2 MD1, MD0 RST VCC VSS C D C E I H H H H F H I/O circuit type* I H Function VCC power input pin for analog circuit. Power (Vref+) input pin for A/D converter. It should be below VCC. General-purpose I/O port. Analog input pins for A/D converter. General-purpose I/O port. Analog input pins for A/D converter. Output pins for PPG. General-purpose I/O port. Trigger input pin for A/D converter. External interrupt request input pin for INT12. General-purpose I/O port (P50 has different I/O circuit type from MB90V340E) . Analog input pins for A/D converter. General-purpose I/O port. Analog input pin for A/D converter. Event input pin for reload timer 3. General-purpose I/O port. Analog input pin for A/D converter. Output pin for reload timer 3 External interrupt request input pin for INT8. General-purpose I/O port. Analog input pins for A/D converter. External interrupt request input pins for INT10, INT11, INT13. Input pin for operation mode specification. Input pins for operation mode specification. Reset input pin. Power input pin (3.5 V to 5.5 V) . Power input pin (0 V) . Power supply stabilization capacitor pin. It should be connected to a higher than or equal to 0.1 F ceramic condenser. (Continued)
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MB90360E Series
Pin No. 27 28
Pin name X0 X1 P27 to P24 IN3 to IN0
I/O circuit type* A Oscillation input pin. Oscillation output pin.
Function
29 to 32
G
General-purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. Event input pins for input capture 0 to 3. General-purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. High current output port. Output pins for PPG. General-purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. High current output port. General-purpose I/O port. Serial data input pin for UART1. General-purpose I/O port. Clock I/O pin for UART1. General-purpose I/O port. Serial data output pin for UART1. General-purpose I/O port. TX output pin for CAN1 interface. General-purpose I/O port. RX input pin for CAN1 interface. External interrupt request input pin for INT9 (Sub) . General-purpose I/O port.
P23, P22 33, 34 PPGF (E) , PPGD (C) J
35, 36
P21, P20
J
37 38 39 40
P85 SIN1 P87 SCK1 P86 SOT1 P43 TX1 P42 RX1 INT9R P83
K F F F
41
F
42
SOT0 TOT2 P84
F
Serial data output pin for UART0. Output pin for reload timer 2. General-purpose I/O port.
43
SCK0 INT15R
F
Clock I/O pin for UART0. External interrupt request input pin for INT15. (Continued)
8
MB90360E Series
(Continued) Pin No. Pin name P82 44 SIN0 INT14R TIN2 45 P44 FRCK0 P40, P41 46, 47 X0A, X1A 48 AVSS B I F F K I/O circuit type* General-purpose I/O port. Serial data input pin for UART0. External interrupt request input pin for INT14. Event input pin for reload timer 2. General-purpose I/O port (Different I/O circuit type from MB90V340E) . Free-run timer 0 clock pin. General-purpose I/O port (Devices with S-suffix and MB90V340E-101/103 only) . Oscillation pins for sub clock (Devices without S-suffix and MB90V340E-102/104 only) . VSS power input pin for analog circuit. Function
* : For the I/O circuit type, refer to " I/O CIRCUIT TYPE".
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MB90360E Series
I/O CIRCUIT TYPE
Type
X1
Circuit
Remarks Oscillation circuit : High-speed oscillation feedback resistor = approx. 1 M
Xout
A
X0
Standby control signal
X1A
Xout
Oscillation circuit : Low-speed oscillation feedback resistor = approx. 10 M
B
X0A
Standby control signal
R
C
CMOS hysteresis inputs
* MASK ROM product : CMOS hysteresis input pin * Flash memory product : CMOS input pin * MASK ROM product : CMOS hysteresis input pin * Flash memory product : - CMOS input pin - No Pull-down
R CMOS hysteresis inputs
D
Pull-down resistor
CMOS hysteresis input pin
E
Pull-up resistor R CMOS hysteresis inputs
(Continued)
10
MB90360E Series
Type
P-ch
Circuit
Remarks * CMOS level output * CMOS hysteresis inputs (With the standby-time input shutdown function) * Automotive input (With the standbytime input shutdown function)
Pout N-ch Nout
F
R CMOS hysteresis inputs
Automotive inputs Standby control for input shutdown
Pull-up control Pull-up resistor P-ch P-ch Pout N-ch Nout
* CMOS level output * CMOS hysteresis inputs (With the standby-time input shutdown function) * Automotive input (With the standbytime input shutdown function)
G
R CMOS hysteresis inputs
Automotive inputs Standby control for input shutdown
P-ch Pout N-ch Nout R
* CMOS level output * CMOS hysteresis inputs (With the standby-time input shutdown function) * Automotive input (With the standbytime input shutdown function) * A/D analog input
H
CMOS hysteresis inputs
Automotive inputs Standby control for input shutdown Analog input
(Continued)
11
MB90360E Series
(Continued) Type
Circuit
Remarks Protection circuit for power supply input
I
P-ch N-ch
Pull-up control Pull-up resistor P-ch P-ch Pout high current output N-ch Nout high current output
* CMOS level output * CMOS hysteresis inputs (With the standby-time input shutdown function) * Automotive input (With the standbytime input shutdown function)
J
R CMOS hysteresis inputs
Automotive inputs Standby control for input shutdown
P-ch Pout N-ch Nout
* CMOS level output * CMOS input (With standby-time input shutdown function) * Automotive input (With standby-time input shutdown function)
K
R CMOS inputs
Automotive inputs Standby control for input shutdown
12
MB90360E Series
HANDLING DEVICES
1. Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions : * A voltage higher than VCC pin or lower than VSS pin is applied to an input or output pin. * A voltage higher than the rated voltage is applied between VCC pin and VSS pin. * The AVCC power supply is applied before the VCC voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. Use meticulous care not to exceed the rating. For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVR) exceed the digital power-supply voltage.
2. Treatment of unused pins
Leaving unused input pins open may result in permanent damage of the device due to misbehavior or latch-up. Therefore, they must be pulled up or pulled down through resistors. In this case, those resistors should be more than 2 k . Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection.
3. Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
MB90360E Series X0
Open
X1
4. Precautions for when not using a sub clock signal
If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin and leave the X1A pin open.
5. Notes on during operation of PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
6. Power supply pins (VCC/VSS)
* If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential are connected the inside of the device to prevent malfunction such as latch-up. To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply and ground externally. * Connect VCC and VSS pins to the device from the current supply source at a low impedance.
13
MB90360E Series
* As a measure against power supply noise, connect a capacitor of about 0.1 F as a bypass capacitor between VCC pin and VSS pin in the vicinity of VCC and VSS pins of the device.
VCC VSS
VCC VSS VCC MB90360E Series
VSS
VCC VSS
VSS
VCC
7. Pull-up/down resistors
The MB90360E Series does not support internal pull-up/down resistors (Port 2 : built-in pull-up resistors) . Use external components where needed.
8. Crystal oscillator circuit
Noises around X0 or X1 pin may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits. It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground area for stabilizing the operation. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
9. Turning-on sequence of power supply to A/D converter and analog inputs
Make sure to turn on the A/D converter power supply (AVCC and AVR) and analog inputs (AN0 to AN15) after turning-on the digital power supply (VCC) . Turn-off the digital power after turning off the A/D converter power supply and analog inputs. In this case, make sure that the voltage does not exceed AVRH or AVCC.
14
MB90360E Series
10. Connection of unused pins of A/D converter if A/D converter is not used
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVR = VSS.
11. Notes on energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 s or more (0.2 V to 2.7 V) .
12. Stabilization of power supply voltage
A sudden change in the power supply voltage may cause the device to malfunction even within the specified VCC power supply voltage operating guarantee range. Therefore, the VCC power supply voltage should be stabilized. For reference, the power supply voltage should be controlled so that VCC ripple variations (peak-to-peak value) at commercial frequencies (50 Hz/60 Hz) fall below 10% of the standard VCC power supply voltage and the coefficient of transient fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
13. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers, turn on the power again.
14. Notes on using CAN function
To use CAN function, please set '1' to DIRECT bit of CAN direct mode register (CDMR) . If DIRECT bit is set to '0' (initial value) , wait states will be performed when accessing CAN registers. Note : Please refer to Hardware Manual of "MB90360E series for detail of CAN Direct Mode Register".
15. Flash security function
The security bit is located in the area of the Flash memory. If protection code 01H is written in the security bit, the Flash memory is in the protected state by security. Therefore, please do not write 01H in this address if you do not use the security function. Please refer to following table for the address of the security bit. Flash memory size MB90F362E MB90F362ES MB90F362TE MB90F362TES MB90F367E MB90F367ES MB90F367TE MB90F367TES Address for security bit
Embedded 512 Kbits Flash Memory
FF0001H
16. Correspondence with TA = +105 C or more
If used exceeding TA = +105 C, please consult with us due to the restricted reliability. It is ensured to write/erase data to the Flash memory between TA = - 40 C and +105 C.
15
MB90360E Series
BLOCK DIAGRAMS
* MB90V340E-101/102
X0, X1 X0A, X1A RST
Clock controller
F2MC-16LX core 16-bit I/O timer 0 Input capture 8 channels
FRCK0 IN7 to IN0
RAM 30 Kbytes Prescaler (5 channels) SOT4 to SOT0 SCK4 to SCK0 SIN4 to SIN0 AVCC AVSS AN23 to AN0 AVRH AVRL ADTG
Output compare 8 channels 16-bit free-run timer 1 CAN controller 3 channels Internal data bus 16-bit reload timer 4 channels
OUT7 to OUT0
FRCK1
UART 5 channels
RX2 to RX0 TX2 to TX0
8/10-bit A/D converter 24 channels
TIN3 to TIN0 TOT3 to TOT0 AD15 to AD00 A23 to A16 ALE RD WRL WRH HRQ HAK RDY CLK
DA01, DA00
10-bit D/A converter 2 channels 8/16-bit PPG 16 channels I2C interface 2 channels DMA
External bus
PPGF to PPG0
SDA1, SDA0 SCL1, SCL0
DTP/ External interrupt Clock monitor
INT15 to INT8 (INT15R to INT8R) INT7 to INT0 CKOT
* : Only for MB90V340E-102
16
MB90360E Series
* MB90V340E-103/104
X0, X1 X0A, X1A* RST
Clock controller/ monitor
F2MC-16LX Core 16-bit I/O timer 0 Input capture 8 channels Output compare 8 channels 16-bit free-run timer 1 CAN controller 3 channels
CR oscillator circuit
FRCK0 IN7 to IN0
RAM 30 Kbytes Prescaler (5 channels) SOT4 to SOT0 SCK4 to SCK0 SIN4 to SIN0 AVCC AVSS AN23 to AN0 AVRH AVRL ADTG
OUT7 to OUT0
FRCK1
UART 5 channels
RX2 to RX0 TX2 to TX0
Internal data bus
8/10-bit A/D converter 24 channels
16-bit reload timer 4 channels
TIN3 to TIN0 TOT3 to TOT0 AD15 to AD00 A23 to A16 ALE RD WRL WRH HRQ HAK RDY CLK
DA01, DA00
10-bit D/A converter 2 channels 8/16-bit PPG 16 channels I2C interface 2 channels DMA
External bus
PPGF to PPG0
SDA1, SDA0 SCL1, SCL0
DTP/ External interrupt Clock monitor
INT15 to INT8 (INT15R to INT8R) INT7 to INT0 CKOT
* : Only for MB90V340E-104
17
MB90360E Series
* MB90F362E/TE/ES/TES, MB90362E/TE/ES/TES
X0, X1 X0A, X1A1 RST Clock controller
F2MC-16LX core
Input capture 4 channels Low voltage/CPU operation detection *2 RAM 3 Kbytes 16-bit free-run timer 0
IN0 to IN3
FRCK0
ROM 64 Kbytes Internal data bus
CAN controller 1 channel 16-bit reload timer 2 channels
RX1 TX1
TIN2, TIN3 TOT2, TOT3
Prescaler (2 channels) SOT0, SOT1 SCK0, SCK1 SIN0, SIN1 AVCC AVSS AN15 to AN0 AVR ADTG
UART 2 channels
8/10-bit A/D converter 16 channels
PPGF(E), PPGD(C), PPGC(D), PPGE(F)
8/16-bit PPG 2 channels
DTP/ External interrupt
INT8, INT9R INT10, INT11 INT12R, INT13 INT14R, INT15R
*1 : Only for devices without S-suffix *2 : Only for devices with T-suffix
18
MB90360E Series
* MB90F367E/TE/ES/TES, MB90367E/TE/ES/TES
X0, X1 X0A, X1A*1 RST
Clock controller/ monitor
F2MC-16LX Core
CR oscillator circuit Low voltage/CPU operation detection *2 RAM 3 Kbytes
Input capture 4 channels 16-bit free-run timer 0
IN0 to IN3
FRCK0
ROM 64 Kbytes Internal data bus
CAN controller 1 channel 16-bit reload timer 2 channels
RX1 TX1
TIN2, TIN3 TOT2, TOT3
Prescaler (2 channels) SOT0, SOT1 SCK0, SCK1 SIN0, SIN1 AVCC AVSS AN15 to AN0 AVR ADTG
UART 2 channels
8/10-bit A/D converter 16 channels
PPGF(E), PPGD(C), PPGC(D), PPGE(F)
8/16-bit PPG 2 channels
DTP/ External interrupt
INT8, INT9R INT10, INT11 INT12R, INT13 INT14R, INT15R
*1 : Only for devices without S-suffix *2 : Only for devices with T-suffix
19
MB90360E Series
MEMORY MAP
MB90F362E/TE/ES/TES MB90362E/TE/ES/TES MB90F367E/TE/ES/TES MB90367E/TE/ES/TES FFFFFFH ROM (FF bank) FF0000H FEFFFFH ROM (FE bank) FE0000H FDFFFFH ROM (FD bank) FD0000H FCFFFFH ROM (FC bank) FC0000H FBFFFFH ROM (FB bank) FB0000H FAFFFFH ROM (FA bank) FA0000H F9FFFFH ROM (F9 bank) F90000H F8FFFFH ROM (F8 bank) F80000H FF0000H FEFFFFH ROM (FF bank)
MB90V340E-101/102 MB90V340E-103/104 FFFFFFH
External access area
00FFFFH 008000H 007FFFH 007900H 0078FFH ROM (image of FF bank) Peripheral
010000H 00FFFFH 008000H 007FFFH 007900H ROM (image of FF bank) Peripheral
RAM 30 Kbytes
000100H
External access area
0000EFH 000000H Peripheral
000CFFH 000100H 0000FFH 0000F0H 0000EFH 000000H
RAM 3 Kbytes
Peripheral
: No access
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referred without using the far specification in the pointer declaration. For example, an attempt to access 00C000H practically accesses the value at FFC000H in ROM. The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00. The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and FF7FFFH is visible only in bank FF. 20
MB90360E Series
I/O MAP
Address 000000H, 000001H 000002H Port 2 Data Register 000003H 000004H Port 4 Data Register 000005H Port 5 Data Register 000006H Port 6 Data Register 000007H 000008H Port 8 Data Register 000009H, 00000AH 00000BH Port 5 Analog Input Enable Register 00000CH Port 6 Analog Input Enable Register 00000DH 00000EH Input Level Select Register 00000FH Input Level Select Register 000010H, 000011H 000012H Port 2 Direction Register 000013H 000014H Port 4 Direction Register 000015H Port 5 Direction Register 000016H Port 6 Direction Register 000017H 000018H Port 8 Direction Register 000019H 00001AH Port A Direction Register 00001BH to 00001DH 00001EH Port 2 Pull-up Control Register 00001FH Register Abbreviation Reserved PDR2 Reserved PDR4 PDR5 PDR6 Reserved PDR8 Reserved ADER5 ADER6 Reserved ILSR0 ILSR1 Reserved DDR2 Reserved DDR4 DDR5 DDR6 Reserved DDR8 Reserved DDRA Reserved PUCR2 Reserved (Continued) R/W Port 2 00000000B W Port A XXX00XXXB R/W Port 8 000000X0B R/W R/W R/W Port 4 Port 5 Port 6 XXX00000B 00000000B 00000000B R/W Port 2 00000000B R/W R/W Ports Ports XXXX0XXXB XXXXXXXXB R/W R/W Port 5, A/D Port 6, A/D 11111111B 11111111B R/W Port 8 XXXXXXXXB R/W R/W R/W Port 4 Port 5 Port 6 XXXXXXXXB XXXXXXXXB XXXXXXXXB R/W Port 2 XXXXXXXXB Access Resource name Initial value
21
MB90360E Series
Address
Register
Abbreviation SMR0 SCR0 RDR0/ TDR0 SSR0 ECCR0 ESCR0 BGR00 BGR01 SMR1 SCR1 RDR1/ TDR1 SSR1 ECCR1 ESCR1 BGR10 BGR11 Reserved
Access W, R/W W, R/W R/W R, R/W R, W, R/W R/W R/W, R R/W, R W, R/W W, R/W R/W R, R/W R, W, R/W R/W R/W, R R/W, R
Resource name
Initial value 00000000B 00000000B 00000000B
000020H Serial Mode Register 0 000021H Serial Control Register 0 000022H Reception/Transmission Data Register 0 000023H Serial Status Register 0 000024H Extended Communication Control Register 0
UART0
00001000B 000000XXB 00000100B 00000000B 00000000B 00000000B 00000000B 00000000B
000025H Extended Status/Control Register 0 000026H Baud Rate Generator Register 00 000027H Baud Rate Generator Register 01 000028H Serial Mode Register 1 000029H Serial Control Register 1 00002AH Reception/Transmission Data Register 1 00002BH Serial Status Register 1 00002CH Extended Communication Control Register 1
UART1
00001000B 000000XXB 00000100B 00000000B 00000000B
00002DH Extended Status/Control Register 1 00002EH Baud Rate Generator Register 10 00002FH Baud Rate Generator Register 11 000030H to 00003AH 00003BH Address Detect Control Register 1 00003CH to 000047H 000048H PPG C Operation Mode Control Register 000049H PPG D Operation Mode Control Register 00004AH 00004BH 00004CH PPG E Operation Mode Control Register 00004DH PPG F Operation Mode Control Register 00004EH 00004FH PPG E/PPG F Count Clock Select Register PPG C/PPG D Count Clock Select Register
PACSR1
R/W
Address Match Detection 1
00000000B
Reserved PPGCC PPGCD PPGCD Reserved PPGCE PPGCF PPGEF Reserved (Continued) W, R/W W, R/W R/W 16-bit PPG E/F 0X000XX1B 0X000001B 000000X0B W, R/W W, R/W R/W 16-bit PPG C/D 0X000XX1B 0X000001B 000000X0B
22
MB90360E Series
Address
Register
Abbreviation ICS01 ICE01 ICS23 ICE23
Access R/W R/W, R R/W R
Resource name Input Capture 0/1 Input Capture 2/3
Initial value 00000000B XXX0X0XXB 00000000B XXXXXXXXB
000050H Input Capture Control Status 0/1 000051H Input Capture Edge 0/1 000052H Input Capture Control Status 2/3 000053H Input Capture Edge 2/3 000054H to 000063H 000064H Timer Control Status 2 000065H Timer Control Status 2 000066H Timer Control Status 3 000067H Timer Control Status 3 000068H A/D Control Status 0 000069H A/D Control Status 1 00006AH A/D Data 0 00006BH A/D Data 1 00006CH ADC Setting 0 00006DH ADC Setting 1 00006EH Low Voltage/CPU Operation Detection Reset Control Register
Reserved TMCSR2 TMCSR2 TMCSR3 TMCSR3 ADCS0 ADCS1 ADCR0 ADCR1 ADSR0 ADSR1 LVRC ROMM Reserved R/W R/W R/W R/W R/W R/W, W R R R/W R/W R/W, W W Low voltage/CPU operation detection reset ROM Mirror A/D Converter 16-bit Reload Timer 2 16-bit Reload Timer 3 00000000B XXXX0000B 00000000B XXXX0000B 000XXXX0B 0000000XB 00000000B XXXXXX00B 00000000B 00000000B 00111000B XXXXXXX1B
00006FH ROM Mirror Function Select 000070H to 00007FH 000080H to 00008FH 000090H to 00009DH 00009EH Address Detect Control Register 0 00009FH Delayed Interrupt/Release Register Low-power Consumption Mode Control Register
Reserved for CAN Interface 1. Refer to " CAN CONTROLLERS"
Reserved Address Match Detection 0 Delayed Interrupt generation module Low-Power consumption Control Circuit Low-Power consumption Control Circuit
PACSR0 DIRR
R/W R/W
00000000B XXXXXXX0B
0000A0H
LPMCR
W, R/W
00011000B
0000A1H Clock Selection Register
CKSCR
R, R/W
11111100B (Continued) 23
MB90360E Series
Address 0000A2H to 0000A7H
Register
Abbreviation
Access
Resource name
Initial value
Reserved WDTC TBTC WTC R, W W, R/W R, R/W Watchdog Timer Timebase Timer Watch Timer XXXXX111B 1XX00100B 1X001000B
0000A8H Watchdog Control Register 0000A9H Timebase Timer Control Register 0000AAH Watch Timer Control register 0000ABH to 0000ADH 0000AEH 0000AFH 0000B0H Interrupt Control Register 00 0000B1H Interrupt Control Register 01 0000B2H Interrupt Control Register 02 0000B3H Interrupt Control Register 03 0000B4H Interrupt Control Register 04 0000B5H Interrupt Control Register 05 0000B6H Interrupt Control Register 06 0000B7H Interrupt Control Register 07 0000B8H Interrupt Control Register 08 0000B9H Interrupt Control Register 09 0000BAH Interrupt Control Register 10 0000BBH Interrupt Control Register 11 0000BCH Interrupt Control Register 12 0000BDH Interrupt Control Register 13 0000BEH Interrupt Control Register 14 0000BFH Interrupt Control Register 15 0000C0H to 0000C9H 0000CAH External Interrupt Enable 1 0000CBH External Interrupt Source 1 0000CCH 0000CDH Detection Level Setting 1 Flash Control Status (Flash Devices only. Otherwise reserved)
Reserved
FMCS
R, R/W
Flash Memory
000X0000B
Reserved ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W Interrupt Control 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B
Reserved ENIR1 EIRR1 ELVR1 EISSR PSCCR R/W R/W R/W R/W W PLL External Interrupt 1 00000000B XXXXXXXXB 00000000B 00000000B 00000000B XXXX0000B (Continued)
0000CEH External Interrupt Source Select 0000CFH PLL/Sub clock Control Register
24
MB90360E Series
Address 0000D0H to 0000FFH 007900H to 007917H
Register
Abbreviation
Access
Resource name
Initial value
Reserved
Reserved PRLLC PRLHC PRLLD PRLHD PRLLE PRLHE PRLLF PRLHF IPCP0 IPCP0 IPCP1 IPCP1 IPCP2 IPCP2 IPCP3 IPCP3 Reserved TCDT0 TCDT0 TCCSL0 TCCSH0 Reserved TMR2/ TMRLR2 TMR3/ TMRLR3 Reserved (Continued) 25 R/W R/W R/W R/W 16-bit Reload Timer 2 16-bit Reload Timer 3 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB R/W R/W R/W R/W I/O Timer 0 00000000B 00000000B 00000000B 0XXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R Input Capture 2/3 Input Capture 0/1 16-bit PPG E/F 16-bit PPG C/D XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
007918H Reload Register LC 007919H Reload Register HC 00791AH Reload Register LD 00791BH Reload Register HD 00791CH Reload Register LE 00791DH Reload Register HE 00791EH Reload Register LF 00791FH Reload Register HF 007920H Input Capture 0 007921H Input Capture 0 007922H Input Capture 1 007923H Input Capture 1 007924H Input Capture 2 007925H Input Capture 2 007926H Input Capture 3 007927H Input Capture 3 007928H to 00793FH 007940H Timer Data 0 007941H Timer Data 0 007942H Timer Control Status 0 007943H Timer Control Status 0 007944H to 00794BH 00794CH 00794DH 00794EH 00794FH 007950H to 00795FH Timer 2/Reload 2 Timer 3/Reload 3
MB90360E Series
Address 007960H 007961H to 00796DH 00796EH 00796FH to 0079DFH
Register Clock Supervisor Control Register
Abbreviation CSVCR
Access R, R/W
Resource name Clock supervisor
Initial value 00011100B
Reserved CAN Direct Mode Register (MB90V340E only)
CDMR
R/W
CAN clock sync
XXXXXXX0B
Reserved PADR0 PADR0 PADR0 PADR1 PADR1 PADR1 PADR2 PADR2 PADR2 Reserved PADR3 PADR3 PADR3 PADR4 PADR4 PADR4 PADR5 PADR5 PADR5 Reserved R/W R/W R/W R/W R/W R/W R/W R/W R/W Address Match Detection 1 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R/W Address Match Detection 0 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
0079E0H Detect Address Setting 0 0079E1H Detect Address Setting 0 0079E2H Detect Address Setting 0 0079E3H Detect Address Setting 1 0079E4H Detect Address Setting 1 0079E5H Detect Address Setting 1 0079E6H Detect Address Setting 2 0079E7H Detect Address Setting 2 0079E8H Detect Address Setting 2 0079E9H to 0079EFH 0079F0H Detect Address Setting 3 0079F1H Detect Address Setting 3 0079F2H Detect Address Setting 3 0079F3H Detect Address Setting 4 0079F4H Detect Address Setting 4 0079F5H Detect Address Setting 4 0079F6H Detect Address Setting 5 0079F7H Detect Address Setting 5 0079F8H Detect Address Setting 5 0079F9H to 007BFFH 007C00H to 007CFFH 007D00H to 007DFFH
Reserved for CAN Interface 1. Refer to " CAN CONTROLLERS"
Reserved for CAN Interface 1. Refer to " CAN CONTROLLERS" (Continued)
26
MB90360E Series
(Continued) Address 007E00H to 007FFFH Register Abbreviation Access Resource name Initial value
Reserved
Notes : * Initial value of "X" represents unknown value. * Any write access to reserved addresses in I/O map should not be performed. A read access to reserved addresses results in reading "X".
27
MB90360E Series
CAN CONTROLLERS
* Conforms to CAN Specification Ver 2.0 Part A and Part B * Supports transmission/reception in standard frame and extended frame formats * Supports transmitting of data frames by receiving remote frames * 16 transmitting/receiving message buffers * 29-bit ID and 8-byte data * Multi-level message buffer configuration * Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as ID acceptance mask * 2 acceptance mask registers in either standard frame format or extended frame formats * Bit rate programmable from 10 kbps/s to 2 Mbps/s (when input clock is at 16 MHz) List of Control Registers (1) Address CAN1 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH Register Message buffer valid register Transmit request register Transmit cancel register Transmission complete register Receive complete register Remote request receiving register Receive overrun register Reception interrupt enable register Abbreviation BVALR TREQR TCANR TCR RCR RRTRR ROVRR RIER Access R/W R/W W R/W R/W R/W R/W R/W Initial Value 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B
28
MB90360E Series
List of Control Registers (2) Address CAN1 007D00H 007D01H 007D02H 007D03H 007D04H 007D05H 007D06H 007D07H 007D08H 007D09H 007D0AH 007D0BH 007D0CH 007D0DH 007D0EH 007D0FH 007D10H 007D11H 007D12H 007D13H 007D14H 007D15H 007D16H 007D17H 007D18H 007D19H 007D1AH 007D1BH Acceptance mask register 1 AMR1 R/W XXXXXXXX XXXXXXXXB Acceptance mask register 0 AMR0 R/W XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB Acceptance mask select register AMSR R/W XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB Register Control status register Last event indicator register Receive and transmit error counter Bit timing register IDE register Transmit RTR register Remote frame receive waiting register Transmit interrupt enable register Abbreviation CSR LEIR RTEC BTR IDER TRTRR RFWTR TIER Access R/W, W R/W, R R/W R R/W R/W R/W R/W R/W Initial Value 0XXXX0X1 00XXX000B 000X0000 XXXXXXXXB 00000000 00000000B 11111111 X1111111B XXXXXXXX XXXXXXXXB 00000000 00000000B XXXXXXXX XXXXXXXXB 00000000 00000000B XXXXXXXX XXXXXXXXB
29
MB90360E Series
List of Message Buffers (ID Registers) Address CAN1 007C00H to 007C1FH 007C20H 007C21H 007C22H 007C23H 007C24H 007C25H 007C26H 007C27H 007C28H 007C29H 007C2AH 007C2BH 007C2CH 007C2DH 007C2EH 007C2FH 007C30H 007C31H 007C32H 007C33H 007C34H 007C35H 007C36H 007C37H 007C38H 007C39H 007C3AH 007C3BH 007C3CH 007C3DH 007C3EH 007C3FH ID register 7 IDR7 R/W XXXXXXXX XXXXXXXXB (Continued) 30 ID register 6 IDR6 R/W XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 5 IDR5 R/W XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 4 IDR4 R/W XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 3 IDR3 R/W XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 2 IDR2 R/W XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 1 IDR1 R/W XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 0 IDR0 R/W XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB Register Abbreviation Access Initial Value XXXXXXXXB to XXXXXXXXB XXXXXXXX XXXXXXXXB
General-purpose RAM
R/W
MB90360E Series
(Continued) Address CAN1 007C40H 007C41H 007C42H 007C43H 007C44H 007C45H 007C46H 007C47H 007C48H 007C49H 007C4AH 007C4BH 007C4CH 007C4DH 007C4EH 007C4FH 007C50H 007C51H 007C52H 007C53H 007C54H 007C55H 007C56H 007C57H 007C58H 007C59H 007C5AH 007C5BH 007C5CH 007C5DH 007C5EH 007C5FH ID register 15 IDR15 R/W XXXXXXXX XXXXXXXXB ID register 14 IDR14 R/W XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 13 IDR13 R/W XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 12 IDR12 R/W XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 11 IDR11 R/W XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 10 IDR10 R/W XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 9 IDR9 R/W XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 8 IDR8 R/W XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB
Register
Abbreviation
Access
Initial Value XXXXXXXX XXXXXXXXB
31
MB90360E Series
List of Message Buffers (DLC Registers and Data Registers) Address CAN1 007C60H 007C61H 007C62H 007C63H 007C64H 007C65H 007C66H 007C67H 007C68H 007C69H 007C6AH 007C6BH 007C6CH 007C6DH 007C6EH 007C6FH 007C70H 007C71H 007C72H 007C73H 007C74H 007C75H 007C76H 007C77H 007C78H 007C79H 007C7AH 007C7BH 007C7CH 007C7DH 007C7EH 007C7FH Register DLC register 0 DLC register 1 DLC register 2 DLC register 3 DLC register 4 DLC register 5 DLC register 6 DLC register 7 DLC register 8 DLC register 9 DLC register 10 DLC register 11 DLC register 12 DLC register 13 DLC register 14 DLC register 15 Abbreviation DLCR0 DLCR1 DLCR2 DLCR3 DLCR4 DLCR5 DLCR6 DLCR7 DLCR8 DLCR9 DLCR10 DLCR11 DLCR12 DLCR13 DLCR14 DLCR15 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued)
32
MB90360E Series
Address CAN1 007C80H to 007C87H 007C88H to 007C8FH 007C90H to 007C97H 007C98H to 007C9FH 007CA0H to 007CA7H 007CA8H to 007CAFH 007CB0H to 007CB7H 007CB8H to 007CBFH 007CC0H to 007CC7H 007CC8H to 007CCFH 007CD0H to 007CD7H 007CD8H to 007CDFH 007CE0H to 007CE7H 007CE8H to 007CEFH
Register Data register 0 (8 bytes) Data register 1 (8 bytes) Data register 2 (8 bytes) Data register 3 (8 bytes) Data register 4 (8 bytes) Data register 5 (8 bytes) Data register 6 (8 bytes) Data register 7 (8 bytes) Data register 8 (8 bytes) Data register 9 (8 bytes) Data register 10 (8 bytes) Data register 11 (8 bytes) Data register 12 (8 bytes) Data register 13 (8 bytes)
Abbreviation
Access
Initial Value XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB (Continued)
DTR0
R/W
DTR1
R/W
DTR2
R/W
DTR3
R/W
DTR4
R/W
DTR5
R/W
DTR6
R/W
DTR7
R/W
DTR8
R/W
DTR9
R/W
DTR10
R/W
DTR11
R/W
DTR12
R/W
DTR13
R/W
33
MB90360E Series
(Continued) Address CAN1 007CF0H to 007CF7H 007CF8H to 007CFFH
Register Data register 14 (8 bytes) Data register 15 (8 bytes)
Abbreviation
Access
Initial Value XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB
DTR14
R/W
DTR15
R/W
34
MB90360E Series
INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt cause Reset INT9 instruction Exception Reserved Reserved CAN 1 reception CAN 1 transmission/node status Reserved Reserved Reserved Reserved 16-bit reload timer 2 16-bit reload timer 3 Reserved Reserved PPG C/D PPG E/F Timebase timer External interrupt 8 to 11 Watch timer External interrupt 12 to 15 A/D converter I/O timer 0 Reserved Reserved Input capture 0 to 3 Reserved UART 0 reception UART 0 transmission UART 1 reception UART 1 transmission EI2OS corresponding N N N N N N N N N N N Y1 Y1 N N N N N Y1 N Y1 Y1 N N N Y1 N Y2 Y1 Y2 Y1 Interrupt vector Number #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H Interrupt control register Number ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 Address 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH (Continued)
35
MB90360E Series
(Continued) Interrupt cause Reserved Reserved Flash memory Delayed interrupt generation module Y1 : Usable Y2 : Usable, with EI2OS stop function N : Unusable Notes : * The peripheral resources sharing the ICR register have the same interrupt level. * When the peripheral resources sharing the ICR register use extended intelligent I/O service, only one can use extended intelligent I/O service at a time. * When either of the 2 peripheral resources sharing the ICR register specifies extended intelligent I/O service, the other one cannot use interrupts. EI2OS corresponding N N N N Interrupt vector Number #39 #40 #41 #42 Address FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt control register Number ICR14 ICR15 Address 0000BEH 0000BFH
36
MB90360E Series
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Symbol VCC Power supply voltage*1 Input voltage*1 Output voltage*
1
Rating Min VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -2.0 -40 -40 -55 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 +2.0 40 15 40 4 30 125 160 40 40 -15 -40 -4 -30 -125 -160 -40 -40 300 +105 +125 +150
Unit V V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mW C C C *7
Remarks
AVCC AVR VI VO ICLAMP |ICLAMP| IOL1 IOL2 IOLAV1 IOLAV2 IOL1 IOL2 IOLAV1 IOLAV2 IOLAV1 IOLAV2 IOH1 IOH2 IOHAV1 IOHAV2 IOH1 IOH2 IOHAV1 IOHAV2 IOHAV1 IOHAV2 PD TA TSTG
VCC = AVCC*2 AVCC AVR*2 *3 *3 *6 *6 *4 *5 *4 *5 *4 *5 *4 +105 C < TA +125 C *5 +105 C < TA +125 C *4 -40 C TA +105 C *5 -40 C TA +105 C *4 *5 *4 *5 *4 *5 *4 +105 C < TA +125 C *5 +105 C < TA +125 C *4 -40 C TA +105 C *5 -40 C TA +105 C
Maximum clamp current Total Maximum clamp current "L" level maximum output current "L" level average output current "L" level maximum overall output current
"L" level average overall output current
"H" level maximum output current "H" level average output current "H" level maximum overall output current
"H" level average overall output current
Power consumption Operating temperature Storage temperature
(Continued)
37
MB90360E Series
(Continued) *1 : This parameter is based on VSS = AVSS = 0 V. *2 : Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC when the power is switched on. *3 : VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However, if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *4 : Applicable to pins : P24 to P27, P40 to P44, P50 to P57, P60 to P67, P80, P82 to P87 *5 : Applicable to pins : P20 to P23 *6 : Applicable to pins : P20 to P27, P40 to P44, P50 to P57, P60 to P67, P80, P82 to P87 * Use within recommended operating conditions. * Use at DC voltage (current) . * The +B signal should always be applied a connecting limit resistance between the +B signal and the microcontroller. * The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. * Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. * Note that if a +B signal is inputted when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. * Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset. * Care must be taken not to leave the +B input pin open. * Recommended circuit sample : * Input/output equivalent circuits Protective diode Limiting resistance +B input (0 V to 16 V)
N-ch VCC P-ch
R
*7 : If used exceeding TA = +105 C, please consult with us due to the restricted reliability. It is ensured to write/erase data to the Flash memory between TA = - 40 C and +105 C. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
38
MB90360E Series
2. Recommended Conditions
(VSS = AVSS = 0 V) Parameter Symbol Value Min 4.0 Power supply voltage VCC, AVCC 3.5 3.0 Typ 5.0 5.0 Max 5.5 5.5 5.5 Unit V V V Remarks Under normal operation Under normal operation when not using the A/D converter and not Flash programming. Maintains RAM data in stop mode Use a ceramic capacitor or comparable capacitor of the AC characteristics. Bypass capacitor at the VCC pin should be greater than this capacitor. *
Smoothing capacitor
CS
0.1
1.0
F
Operating temperature
TA
-40 -40

+105 +125
C C
* : If used exceeding TA = +105 C, please consult with us due to the restricted reliability. It is ensured to write/erase data to the Flash memory between TA = - 40 C and +105 C. * C Pin Connection Diagram
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
39
MB90360E Series
3. DC Characteristics
(TA = -40 C to +125 C, VCC = 5.0 V 10%, fCP 24 MHz, VSS = AVSS = 0 V) Parameter Symbol Pin Condition Value Min Typ Max VCC + 0.3 Unit Remarks Pin inputs if CMOS hysteresis input levels are selected (except P82, P85) Pin inputs if Automotive input levels are selected P82, P85 inputs if CMOS input levels are selected RST input pin (CMOS hysteresis) MD input pin Pin inputs if CMOS hysteresis input levels are selected (except P82, P85) Pin inputs if Automotive input levels are selected P82, P85 inputs if CMOS input levels are selected RST input pin (CMOS hysteresis) MD input pin
VIHS
0.8 VCC
V
VIHA Input "H" voltage VIHS
0.8 VCC
VCC + 0.3
V

0.7 VCC

VCC + 0.3 VCC + 0.3 VCC + 0.3 0.2 VCC
V
VIHR VIHM
0.8 VCC VCC - 0.3 VSS - 0.3
V V
VILS
V
VILA Input "L" voltage VILS
VSS - 0.3
0.5 VCC
V

VSS - 0.3 VSS - 0.3 VSS - 0.3 VCC - 0.5
50
0.3 VCC
V
VILR VILM Output "H" voltage VOH VOHI VOL VOLI IIL RUP
0.2 VCC VSS + 0.3 0.4 0.4 +1 100
V V V V V V A k
Other than VCC = 4.5 V, P20 to P23 IOH = -4.0 mA P20 to P23
VCC = 4.5 V, VCC - 0.5 IOH = -14.0 mA -1 25
Output "L" voltage Input leak current Pull-up resistance
Other than VCC = 4.5 V, P20 to P23 IOL = 4.0 mA P20 to P23 P20 to P27, RST VCC = 4.5 V, IOL = 20.0 mA VCC = 5.5 V, VSS < VI < VCC
(Continued)
40
MB90360E Series
(TA = -40 C to +125 C, VCC = 5.0 V 10%, fCP 24 MHz, VSS = AVSS = 0 V) Parameter Pull-down resistance Symbol RDOWN Pin Condition Value Min 25 Typ 50 Max 100 Unit Remarks
MB90362E, MB90362ES, MB90362TE, MB90362TES
MD2
VCC = 5.0 V, Internal frequency : 24 MHz, At normal operation.
k
35
45
mA
ICC
VCC = 5.0 V, Internal frequency : 24 MHz, At writing Flash memory. VCC = 5.0 V, Internal frequency : 24 MHz, At erasing Flash memory.
50
60
mA
Flash memory devices Flash memory devices
50
60
mA
ICCS
VCC = 5.0 V, Internal frequency : 24 MHz, At sleep mode. VCC = 5.0 V, Internal frequency : 2 MHz, At main timer mode VCC = 5.0 V, Internal frequency : 24 MHz, At PLL timer mode, External frequency = 4 MHz VCC
Stopping clock supervisor

12 0.3 0.4
20 0.8
mA
Devices without T-suffix Devices with T-suffix
ICTS
mA 1.0
ICTSPLL6 Power supply current*
4
7
mA

40
100
ICCL
VCC = 5.0 V Internal frequency : 8 kHz, At sub operation, TA = +25C
MB90F362E, MB90F367E, MB90362E, MB90367E MB90F367E, MB90367E MB90F362TE, MB90F367TE, MB90362TE, MB90367TE MB90F367TE, MB90367TE MB90F362E, MB90F367E, MB90362E, MB90367E MB90F367E, MB90367E MB90F362TE, MB90F367TE, MB90362TE, MB90367TE MB90F367TE, MB90367TE
Operating clock supervisor Stopping clock supervisor Operating clock supervisor Stopping clock supervisor
60
150 A
90
200
110
250
10
50
ICCLS
VCC = 5.0 V Internal frequency : 8 kHz, At sub sleep, TA = +25C
Operating clock supervisor Stopping clock supervisor Operating clock supervisor
30
100 A
60
150
80
200
(Continued) 41
MB90360E Series
(Continued) Symbol (TA = -40 C to +125 C, VCC = 5.0 V 10%, fCP 24 MHz, VSS = AVSS = 0 V) Pin Condition Value Min Typ 8 Max 30 Unit Remarks
MB90F362E, MB90F367E, MB90362E, MB90367E MB90F367E, MB90367E MB90F362TE, MB90F367TE, MB90362TE, MB90367TE MB90F367TE, MB90367TE
Parameter
Stopping clock supervisor
ICCT Power supply current* VCC
VCC = 5.0 V Internal frequency : 8 kHz, At watch mode, TA = +25C
Operating clock supervisor Stopping clock supervisor Operating clock supervisor
30
70 A
60
130
80 5 50
170 25 130 A A
ICCH
VCC = 5.0 V, At stop mode, TA = +25C
Other than AVCC, AVSS, AVR, VCC, VSS, C
Devices without T-suffix Devices with T-suffix
Input capacity
CIN
5
15
pF
* : The power supply current is measured with an external clock.
42
MB90360E Series
4. AC Characteristics
(1) Clock Timing (TA = -40 C to +125 C, VCC = 5.0 V 10%, fCP 24 MHz, VSS = AVSS = 0 V) Parameter Symbol Pin Value Min 3 4 4 X0, X1 4 4 4 Clock frequency fC 3 4 4 X0, X1 4 4 4 fCL Clock cycle time tCYL tCYLL Input clock pulse width Input clock rise and fall time Internal operating clock frequency (machine clock) Internal operating clock cycle time (machine clock) PWH, PWL PWHL, PWLL tCR, tCF fCP fCPL tCP tCPL X0A, X1A X0, X1 X0, X1 X0A, X1A X0 X0A X0 -- 62.5 41.67 10 10 5 1.5 41.67 20 32.768 30.5 15.2 8.192 122.1 8 6 4 100 333 333 -- 5 24 50 666 MHz MHz MHz kHz ns ns s ns s ns Duty ratio is about 30% to 70%. When using external clock When using an oscillation circuit When using an external clock 24 24 12 MHz MHz MHz 8 6 4 MHz MHz MHz Typ Max 16 16 12 Unit MHz MHz MHz Remarks 1/2 when PLL stops, When using an oscillation circuit PLL x 1, When using an oscillation circuit PLL x 2, When using an oscillation circuit PLL x 3, When using an oscillation circuit PLL x 4, When using an oscillation circuit PLL x 6, When using an oscillation circuit 1/2 when PLL stops, When using an external clock PLL x 1, When using an external clock PLL x 2, When using an external clock PLL x 3, When using an external clock PLL x 4, When using an external clock PLL x 6, When using an external clock
MHz When using main clock kHz ns s When using sub clock When using main clock When using sub clock
43
MB90360E Series
* Clock Timing
tCYL
X0
PWH tCF PWL tCR
0.8 VCC 0.2 VCC
tCYLL
X0A
PWHL tCF PWLL tCR
0.8 VCC 0.2 VCC
44
MB90360E Series
* Guaranteed PLL Operation Range
Guaranteed operation range 5.5 Power supply voltage VCC (V) 4.0 3.5 Guaranteed PLL operation range Guaranteed A/D converter operation range
1.5
4 Internal clock fCP (MHz)
24
Guaranteed operation range of MB90360E series
Guaranteed oscillation frequency range 24 x6 x4 x3 x2 x1
Internal clock fCP (MHz)
16 12 8 4.0 1.5 34 8 12 16 24 x1/2 (PLL off)
External clock fC (MHz) *
* : When using the oscillation circuit, the maximum oscillation clock frequency is 16 MHz.
45
MB90360E Series
(2) Reset Standby Input (TA = -40 C to +125 C, VCC = 5.0 V 10%, fCP 24 MHz, VSS = AVSS = 0 V) Parameter Symbol Pin Value Min 500 Reset input time tRSTL RST Oscillation time of oscillator* + 100 s 100 Max Unit ns ns s Remarks Under normal operation In stop mode, sub clock mode, sub sleep mode, and watch mode In timebase timer mode
* : Oscillation time of oscillator is the time that the amplitude reaches 90%. In the crystal oscillator, the oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of s and several ms. With an external clock, the oscillation time is 0 ms. * Under normal operation :
tRSTL
RST
0.2 VCC 0.2 VCC
* In stop mode, sub clock mode, sub sleep mode, and watch mode :
tRSTL
RST
0.2 VCC 90% of amplitude 0.2 VCC
X0
Internal operation clock
Oscillation time of oscillator
100 s Oscillation stabilization waiting time Instruction execution
Internal reset
46
MB90360E Series
(3) Power-on Reset (TA = -40 C to +125 C, VCC = 5.0 V 10%, fCP 24 MHz, VSS = AVSS = 0 V) Parameter Power on rise time Power off time Symbol tR tOFF Pin VCC VCC Condition Value Min 0.05 1 Max 30 Unit ms ms Due to repetitive operation Remarks
tR 2.7 V 0.2 V 0.2 V tOFF 0.2 V
VCC
Note : If you change the power supply voltage too rapidly, a power-on reset may occur. We recommend that you start up smoothly by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within 1 V/s, you can operate while using the PLL clock.
VCC 3V VSS
Holds RAM data We recommend a rise of 50 mV/ms maximum.
47
MB90360E Series
(4) UART0/UART1 (TA = -40 C to +125 C, VCC = 5.0 V 10%, fCP 24 MHz, VSS = 0 V) Value Pin Condition Unit Min Max SCK0, SCK1 SCK0, SCK1, SOT0, SOT1 SCK0, SCK1, SIN0, SIN1 SCK0, SCK1, SIN0, SIN1 SCK0, SCK1 SCK0, SCK1 SCK0, SCK1, SOT0, SOT1 SCK0, SCK1, SIN0, SIN1 SCK0, SCK1, SIN0, SIN1 External shift clock mode output pins : CL = 80 pF + 1 TTL. Internal shift clock mode output pins : CL = 80 pF + 1 TTL. 8 tCP -80 100 60 4 tCP 4 tCP 60 60 +80 150 ns ns ns ns ns ns ns ns ns
Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK Valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK Valid SIN hold time
Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX
Notes : * AC characteristic in CLK synchronized mode. * CL is load capacity value of pins when testing. * tCP is internal operating clock cycle time (machine clock) . Refer to " (1) Clock Timing". * Internal Shift Clock Mode
tSCYC
SCK
2.4 V 0.8 V
tSLOV
0.8 V
SOT
2.4 V 0.8 V tIVSH tSHIX VIH VIL
SIN
VIH VIL
48
MB90360E Series
* External Shift Clock Mode
tSLSH tSHSL VIH VIL tSLOV VIL VIH
SCK
SOT
2.4 V 0.8 V tIVSH tSHIX VIH VIL
SIN
VIH VIL
(5) Trigger Input Timing (TA = -40 C to +125 C, VCC = 5.0 V 10%, fCP 24 MHz, VSS = 0 V) Value Pin Condition Unit Min Max INT8, INT9R INT10, INT11 INT12R, INT13 INT14R, INT15R ADTG
Parameter
Symbol
Input pulse width
tTRGH tTRGL
5 tCP
ns
Note : tCP is internal operating clock cycle time (machine clock) . Refer to " (1) Clock Timing".
INT8, INT9R INT10, INT11 INT12R, INT13 INT14R, INT15R ADTG
VIH
VIH VIL tTRGH tTRGL VIL
49
MB90360E Series
(6) Timer Related Resource Input Timing (TA = -40 C to +125 C, VCC = 5.0 V 10%, fCP 24 MHz, VSS = 0 V) Value Parameter Symbol Pin Condition Unit Min Max Input pulse width tTIWH tTIWL TIN2, TIN3 IN0 to IN3 4 tCP ns
Note : tCP is internal operating clock cycle time (machine clock) . Refer to " (1) Clock Timing".
VIH
VIH VIL tTIWH tTIWL VIL
TIN2, TIN3 IN0 to IN3
(7) Timer Related Resource Output Timing (TA = -40C to +125C, VCC = 5.0 V 10%, fCP 24 MHz, VSS = 0 V) Value Parameter Symbol Pin Condition Unit Min Max CLK TOUT change time tTO TOT2, TOT3 PPGC to PPGF 30 ns
CLK
2.4 V
TOT2, TOT3 PPGC to PPGF
2.4 V 0.8 V
tTO
50
MB90360E Series
5. A/D Converter
(TA = -40 C to +125 C, 3.0 V AVR - AVSS, VCC = AVCC = 5.0 V 10%, fCP 24 MHz, VSS = AVSS = 0 V) Parameter Resolution Total error Nonlinearity error Differential nonlinearity error Zero reading voltage Full scale reading voltage Compare time Sampling time Analog port input current Analog input voltage range Reference voltage range Power supply current Reference voltage supply current Offset between input channels Symbol VOT VFST IAIN VAIN IA IAH IR IRH Pin Value Min Typ Max 10 3.0 2.5 1.9 Unit bit LSB LSB LSB V V s s A V V mA A A A LSB * * 4.5 V AVCC 5.5 V 4.0 V AVCC < 4.5 V 4.5 V AVCC 5.5 V 4.0 V AVCC < 4.5 V Remarks
AN0 to AN15 AVSS - 1.5 AVSS + 0.5 AVSS + 2.5 AN0 to AN15 AVR - 3.5 AVR - 1.5 AVR + 0.5 AN0 to AN15 AN0 to AN15 AVR AVCC AVCC AVR AVR AN0 to AN15 1.0 2.0 0.5 1.2 -0.3 AVSS AVSS + 2.7 3.5 600 16500
+0.3 AVR AVCC 7.5 5 900 5 4
* : If A/D converter is not operating, a current when CPU is stopped is applicable (VCC = AVCC = AVR = 5.0 V) .
51
MB90360E Series
* About the external impedance of analog input and its sampling time A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage changed to the internal sample and hold capacitor is insufficient, adversely affecting A/ D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. And, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin. * Analog input equivalent circuit model
R
Analog input
C
Comparator During sampling : ON MB90F362E/TE/ES/TES, MB90F367E/TE/ES/TES R C 2.0 k (Max) 16.0 pF (Max) 4.5 V AVCC 5.5 V 4.0 V AVCC < 4.5 V 8.2 k (Max) 16.0 pF (Max) MB90362E/TE/ES/TES, MB90367E/TE/ES/TES, MB90V340E-101/102/103/104 R 4.5 V AVCC 5.5 V 2.0 k (Max) 4.0 V AVCC < 4.5 V 8.2 k (Max)
C 14.4 pF (Max) 14.4 pF (Max)
Note : The values are reference values.
52
MB90360E Series
* The relationship between external impedance and minimum sampling time * At 4.5 V AVCC 5.5 V (External impedance = 0 k to 100 k)
MB90362E/TE/ES/TES, MB90367E/TE/ES/TES, MB90V340E-101/102/103/104
(External impedance = 0 k to 20 k)
MB90362E/TE/ES/TES, MB90367E/TE/ES/TES, MB90V340E-101/102/103/104
External impedance [k]
External impedance [k]
100 90 80 70 60 50 40 30 20 10 0 0
20 18 16 14 12 10 8 6 4 2 0 0
MB90F362E/TE/ES/TES MB90F367E/TE/ES/TES
MB90F362E/TE/ES/TES MB90F367E/TE/ES/TES
5
10
15
20
25
30
35
1
2
3
4
5
6
7
8
Minimum sampling time [s] * At 4.0 V AVCC < 4.5 V (External impedance = 0 k to 100 k)
MB90362E/TE/ES/TES, MB90367E/TE/ES/TES, MB90V340E-101/102/103/104
Minimum sampling time [s]
(External impedance = 0 k to 20 k)
MB90362E/TE/ES/TES, MB90367E/TE/ES/TES, MB90V340E-101/102/103/104
External impedance [k]
100 90 80 70 60 50 40 30 20 10 0 0
External impedance [k]
MB90F362E/TE/ES/TES MB90F367E/TE/ES/TES
20 18 16 14 12 10 8 6 4 2 0 0
MB90F362E/TE/ES/TES MB90F367E/TE/ES/TES
5
10
15
20
25
30
35
1
2
3
4
5
6
7
8
Minimum sampling time [s]
Minimum sampling time [s]
* About errors As | AVR - AVSS | becomes smaller, values of relative errors grow larger.
53
MB90360E Series
6. Definition of A/D Converter Terms
Resolution Non linearity error Differential linearity error Total error : Analog variation that is recognized by an A/D converter. : Deviation between a line across zero-transition line ( "00 0000 0000B" "00 0000 0001B" ) and full-scale transition line ( "11 1111 1110B" "11 1111 1111B" ) and actual conversion characteristics. : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. : Difference between an actual value and an theoretical value. A total error includes zero transition error, full-scale transition error, and linear error.
Total error
3FFH 3FEH 3FDH Digital output {1 LSB x (N - 1) + 0.5 LSB} Actual conversion characteristics 1.5 LSB
004H 003H 002H 001H 0.5 LSB AVSS Analog input
VNT (Actually-measured value) Actual conversion characteristics Ideal characteristics
AVR
Total error of digital output "N" = 1 LSB (Ideal value) =
VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB AVR - AVSS [V] 1024
[LSB]
N : A/D converter digital output value VOT (Ideal value) = AVSS + 0.5 LSB [V] VFST (Ideal value) = AVR - 1.5 LSB [V] VNT : A voltage at which digital output transits from (N - 1) to N.
(Continued)
54
MB90360E Series
(Continued) Non linearity error
3FFH 3FEH 3FDH Digital output Actual conversion characteristics {1 LSB x (N - 1) + VOT } N + 1H VFST (actual measurement value) VNT (actual measurement value) Actual conversion characteristics Actual conversion characteristics
Differential linearity error
Ideal characteristics
Digital output
NH
004H 003H 002H
N - 1H
V (N + 1) T (actual measurement value) VNT (actual measurement value) Actual conversion characteristics AVR Analog input
Ideal characteristics 001H VOT (actual measurement value) AVSS Analog input AVR
N - 2H
AVSS
Non linearity error of digital output N = Differential linearity error of digital output N = 1 LSB =
VNT - {1 LSB x (N - 1) + VOT} 1 LSB V (N+1) T - VNT 1 LSB VFST - VOT 1022 -1 LSB [LSB] [V]
[LSB]
N : A/D converter digital output value VOT : Voltage at which digital output transits from "000H" to "001H." VFST : Voltage at which digital output transits from "3FEH" to "3FFH."
55
MB90360E Series
7. Flash Memory Program/Erase Characteristics
Parameter Chip erase time Word (16-bit width) programming time Program/Erase cycle Flash memory data retention time Conditions Value Min 10000 20 Typ 1 16 Max 15 3600 Unit s s cycle year * Remarks Excludes programming prior to erasure Except for the overhead time of the system level
TA = -40 C to +105 C VCC = 5.0 V Average TA = +85 C
* : Corresponding value comes from the technology reliability evaluation result (using Arrhenius equation to translate high temperature measurements into normalized value at +85 C) .
56
MB90360E Series
ORDERING INFORMATION
Part number MB90F362EPMT MB90F362TEPMT MB90F362ESPMT MB90F362TESPMT MB90F367EPMT MB90F367TEPMT MB90F367ESPMT MB90F367TESPMT MB90362EPMT MB90362TEPMT MB90362ESPMT MB90362TESPMT MB90367EPMT MB90367TEPMT MB90367ESPMT MB90367TESPMT MB90V340E-101 MB90V340E-102 MB90V340E-103 MB90V340E-104 299-pin ceramic PGA (PGA-299C-A01) For evaluation 48-pin plastic LQFP (FPT-48P-M26) Package Remarks
57
MB90360E Series
PACKAGE DIMENSION
48-pin plastic LQFP Lead pitch Package width x package length Lead shape Sealing method Mounting height Weight 0.50 mm 7 x 7 mm Gullwing Plastic mold 1.70 mm MAX 0.17 g P-LFQFP48-7x7-0.50
(FPT-48P-M26)
Code (Reference)
48-pin plastic LQFP (FPT-48P-M26)
Note 1) * : These dimensions include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
9.000.20(.354.008)SQ
* 7.00 -0.10 .276 -.004 SQ
36 25
+0.40
+.016
0.1450.055 (.006.002)
37
24
0.08(.003) INDEX
Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
48
13
"A" 0~8 LEAD No. 0.50(.020)
1 12
0.100.10 (.004.004) (Stand off)
0.200.05 (.008.002)
0.08(.003)
M
0.25(.010) 0.600.15 (.024.006)
C
2003 FUJITSU LIMITED F48040S-c-2-2
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
58
MB90360E Series
MAIN CHANGES IN THIS EDITION
Page 1 2 26 41
DESCRIPTION FEATURES I/O MAP ELECTRICAL CHARACTERISTICS
Section
Change Results Added the following part numbers. (MB90367E(S)/TE(S), MB90F367E(S)/TE(S), MB90V340E-103/104) Added a description of the "Clock supervisor". Added a description of the "Clock supervisor". Added the "Clock supervisor Control Register". Added the ratings for the "Clock supervisor" to the "ICCL" section of the power supply current ratings. Added the ratings for the "Clock supervisor" to the "ICCLS" section of the power supply current ratings.
3. DC Characteristics
42
Added the ratings for the "Clock supervisor" to the "ICCT" section of the power supply current ratings.
The vertical lines marked in the left side of the page show the changes.
59
MB90360E Series
The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept.
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